![]() ![]() # Targeting FPGA bitstream zcu102_single. # Compiling network for Deep Learning FPGA prototyping. To program the device, use the installed Xilinx Vivado Design Suite over an Ethernet connection. Interface options are JTAG (default) and Ethernet. YPred = transform(testDSTrans, = readall(YPred, "UseParallel",pctExists) Ĭreate a target object for your target device that has a vendor name and an interface to connect your target device to the host computer. TestFrames = transform(testDSTrans, = readall(testFrames, "UseParallel",pctExists) ValidLabels = transform(validDSTrans, = readall(validLabels, "UseParallel",pctExists) TrainLabels = transform(trainDSTrans, = readall(trainLabels, "UseParallel",pctExists) % Read the training and validation labels into the memory If contains(char(modulationTypes(modType)), ) Modulator = helperModClassGetModulator(modulationTypes(modType), sps, fs) NumSymbols = (numFramesPerModType / sps) ĭataSrc = helperModClassGetSource(modulationTypes(modType), sps, 2*spf, fs) = mkdir(dataDirectory) įprintf( '%s - Generating %s frames\n'. If length(files) = numModulationTypes*numFramesPerModTypeĭisp( "Generating data and saving in data files.") For this example, assume a maximum clock offset of 5 ppm.įiles = dir(fullfile(dataDirectory,sprintf( "%s*",fileNameRoot))) Clock offset is measured in parts per million (ppm). For each frame, the channel generates a random Δclock value from a uniformly distributed set of values in the range, where maxΔclock is the maximum clock offset. ![]() The channel simulator uses the clock offset factor C, expressed as C=1 Δclock106, where Δclock is the clock offset. ![]() Clock offset causes the center frequency, which is used to downconvert the signal to baseband, and the digital-to-analog converter sampling rate to differ from theoretical values. Implement the channel by using the following settings.Ĭlock offset occurs because of the inaccuracies of internal clock sources of transmitters and receivers. The K-factor is 4 and the maximum Doppler shift is 4 Hz, which is equivalent to a walking speed at 902 MHz. Assume a delay profile of samples that have corresponding average path gains of dB. The channel passes the signals through a Rician multipath fading channel by using the comm.RicianChannel (Communications Toolbox) (Communications Toolbox) System object. Implement the channel by using the awgn (Communications Toolbox) (Communications Toolbox) function. The channel adds AWGN by using an SNR of 30 dB. Plot the scores.Ĭlock offset, resulting in center frequency offset and sampling time driftīecause the network in this example makes decisions based on single frames, each frame must pass through an independent channel AWGN. The score corresponds to the probability that each frame has the predicted modulation type. The classifier also returns a vector of scores for each frame. For details on the generation of the modulated signals, see the helperModClassGetModulator function. The network correctly identifies the frames as PAM4 frames. Return the classifier predictions, which are analogous to hard decisions. UnknownFrames = helperModClassGetNNFrames(rx) OutTimeDrift = interp1(t, outFreqShifter, tp) OutFreqShifter = frequencyShifter(outMultipathChan) 'SampleRate', fs) ĬlockOffset = (rand() * 2*maxOffset) - maxOffset įrequencyShifter.FrequencyOffset = -(C-1)*fc 'MaximumDopplerShift', 4) įrequencyShifter = comm.PhaseFrequencyOffset(. Tx = filter(filterCoeffs,1,upsample(syms,8)) % Set the random number generator to a known state to be able to regenerate % the same frames every time the simulation is run
0 Comments
Leave a Reply. |